With each succeeding generation of integrated circuit technology, variability is proportionately increasing. The sources of such variability include manufacturing variations, device fatigue, environmental variations and phase-locked loop (PLL) variations. In the case of manufacturing variations, the front-end-of-the-line (FEOL) which are the layers that define the active transistors show variation in the transistor's electrical characteristics. Physical quantities such as the length of the gate, depth of the semiconductor junction or thickness of the oxide cannot be perfectly controlled during manufacturing and hence show variations, which lead to variations in the behavior of the transistors. Moreover, as the physical dimensions get smaller in modern technologies, variability is proportionately increasing. In addition, the back-end-of-the-line (BEOL), which consists of the metal interconnect layers, also exhibits variability. For example, the thickness, width and inter-layer dielectric thickness of each metal layer are sources of variability. These, in turn, cause the wires to change their delay, and in fact these sources of variability can change the delay of gates which are driving them and gates which are driven by them.
A second type of variations is due to device fatigue effects such as hot electron and negative bias temperature instability (NBTI). After a long period of use in the field, for example, transistor characteristics change due to these physical phenomena, leading to changes in the delay of circuit components.
A third type of variations is due to environmental effects such as temperature and power supply voltage. A fourth type of variations is PLL variations which can include PLL jitter and duty-cycle variability.
It is to be noted that in addition to the above, there are other sources of variation such as model-to-hardware miscorrelation, silicon-on-insulator (SOI) history effects and coupling noise. These other types of variation can also be considered during statistical timing analysis of digital integrated circuits.
The variation of delays shown by gates and wires in an integrated circuit can be classified in many different ways. The variation may be from batch-to-batch during the manufacturing, wafer-to-wafer, chip-to-chip or within a single chip. Lens aberration effects during photolithography, for example, can cause variation of the effective length of transistors across a reticle field. There can be temperature and power supply voltage variations across a chip. The variations can also be classified by the time scales during which variability develops. For instance, fatigue effects cause variability over a period of years, whereas across the chip, temperature or power supply gradients can develop over seconds or milliseconds, and coupling noise variations can occur in nanoseconds or picoseconds. Whichever way the variations of delays are classified, it is abundantly clear that these sources of variation are making integrated circuit analysis and design more difficult and must be accurately accounted for during timing analysis.
The traditional timing methodology to handle such variability is to conduct multiple static timing analyses at different “cases” or “corners” to determine the spread of performance of the circuit under these variations. Corners may include, for example, “best case,” “nominal” and “worst case.” Unfortunately, the traditional methodology is breaking down because the number of independent and significant sources of variation is numerous, and too many timing runs would be required. One way to combat this is to worst-case or guard-band against some sources of variation, but this causes pessimism in the performance prediction. Another way to combat the explosion of timing runs required is to skip the analysis at certain corners, but this is risky since the performance of the circuit may be unacceptable at the skipped corners and this may be manifested by chips failing on the tester or in the field. Because of these effects, traditional timing methodologies are rapidly becoming burdensome, as well as risky and pessimistic at the same time.
Moreover, for a thorough analysis, several combinations of process variations must be analyzed. For example, weak and strong drivers, thin and thick metal layers, high and low voltage supplies, and all combinations thereof should be examined for a thorough analysis. Such an exhaustive analysis, however, is inefficient.
A solution to the problems faced by traditional timing methodologies is statistical or probabilistic timing analysis. With each new generation of integrated circuit technology, variability (e.g., due to process parameters, environmental parameters and aging effects, hereinafter collectively referred to as “process parameters”) is proportionately increasing. To handle this increased variability in static timing analysis (STA) efficiently and with reduced pessimism compared to corner-based (or deterministic) timing methods, statistical timing is often used. Statistical timing analysis is static timing analysis that accounts for process variation; as used herein, the terms “static timing analysis”, or simply “timing analysis”, are understood to include statistical timing analysis. In such an analysis, timing quantities such as delays, arrival times and slacks are not treated as single numbers, but rather as probability distributions. Thus the full probability distribution of the performance of the circuit under the influence of variations may be predicted by a single timing run. Moreover, the problems of unnecessary risk, excessive timing runs and pessimism are all potentially avoided.
In addition to accounting for variations, e.g., process variations, in a timing analysis, coupling capacitance should also be accounted for in the timing analysis. Coupling capacitance exists when two neighboring wires in an integrated circuit are in close proximity to each other. Depending on how the signals rise or fall on these wires, capacitive coupling can cause changes in the delays and slews (transition times) of gates and wires. For example, if the signals on the two neighboring wires are switching in the same direction (e.g., both rising or both falling), then the coupling capacitances between the two wires have their two terminal voltages moving in the same direction; hence the effective capacitance is reduced due to the so-called Miller effect, which causes the signals to speed up. Alternatively, if the two signals are switching in opposite directions, the effective capacitance is exacerbated, which can cause the signals to slow down. In order to accurately predict the coupling capacitance, a K-factor/Miller-cap multiplier may be determined. The Miller-cap multiplier represents the amount by which the effect of the coupling capacitance on the net increases or decreases due to switching on the net to which it is coupled. Taking into account these coupling effects is essential to correctly predict the timing characteristics of integrated circuits. Moreover, with advanced technologies, coupling between wires is increasing, since the wires in modern integrated circuit technologies are taller and thinner than ever before, and high packing densities lead to wires that are closer to each other and to a larger number of on-chip interconnections.
In addition to the drawbacks of deterministic STA due to its inability to efficiently account for, e.g., process variations in a timing analysis, there are several other drawbacks of STA with regard to accounting for coupling capacitances. For example, coupling in the form of interactions between adjacent wires causes disturbances that are not easily handled by a conventional static timing analysis. This is because static timing analysis relies on levelization of the timing graph, whereas due to coupling, gates and wires at different level numbers can impact each others' delays and slews. Although some methods are known for analyzing coupling effects in STA, these methods do not take process variations into account.
Additionally, predicting the worst-case corner (or setting of process parameters that produces the worst-case timing result) is not immediately obvious, since when process parameters vary, some of the factors described above make the coupling event worse, and some factors make it better. For example, suppose that, due to process variations, the victim driving gate strength is diminished. As a result of this variation, the victim near-end and far-end signals arrive later. One possible result is an overlapping time window between the victim and aggressor, which will make the coupling event worse. A different, but also possible, result is that there will no longer be an overlapping time window, which will make the coupling event better.
Furthermore, using a worst-case analysis is needlessly pessimistic. For example, suppose again that, due to process variations, the victim driving gate strength is diminished. As a result, the victim near-end and far-end signals arrive later, and perhaps there will be no overlapping time window between the aggressor and victim. On the other hand, if the victim driving gate is stronger, the impact of the noise coupling event will be diminished, since the strong driving gate will drive the wire in a stronger fashion. A simple worst-case analysis will not take these correlations into account and will predict a needlessly pessimistic result.
Additionally, the delays of edges in a timing graph typically reflect the delay through either a block (circuit) in the system, or from the source to a sink of a net in the system. In a system implemented with CMOS integrated circuits both of these delays will typically depend on the capacitive load on the net being driven by a block or whose delay is being computed, and on the signal slew (defined as the transition time or rise or fall time) at the source node of the edge. Traditionally, the capacitive load has been assumed to be a capacitance coupled to ground. However, in modern integrated circuits, the wires comprising the nets of the integrated circuit are physically very close together. Consequently, the coupling capacitance between the nets of the integrated circuit is often greater than the capacitance from the net to ground. Since these neighboring wires will be switching, the grounded capacitance assumption is invalid.
As a statistical static timing analysis (SSTA) is performed using K-factors to account for coupling capacitances, the K-factors may alter the SSTA, which in turn may alter the K-factors. Thus, performing an SSTA wherein the K-factors are dynamically adjusted involves an iterative process that may involve a large number of calculations. Thus, integrating the coupling iterative process within a statistical static timing analysis (SSTA) would necessitate a long processing time, and consequently, increase costs and reduce efficiency.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.